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DS04-21314-1E
DATA SHEET
MB1519 ASSP
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 600MHz PRESCALER
The Fujitsu MB1519 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer designed for cellular telephone and cordless telephone applications. The MB1519 has two PLL circuits on a single chip: one for transmit and the other for reception. Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit PLL contains a low sensitivity charge pump for ease of modulation and reception PLL contains a high sensitivity charge pump for faster lock up time. 600 MHz dual modulus prescalers are on chip and enables a pulse swallow function. It operates supply voltage of 3.0V typ. and dissipates 11mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
PLASTIC PACKAGE DIP-20P-M02
* * * * * *
High operating frequency: fin = 600MHz Low power supply voltage: VCC = 2.7 to 5.5V Low power supply current: ICC = 11mA typ, @3V. Wide operating temperature: TA = -40 to 85C Two charge pumps Low sensitivity charge pump for transmit High sensitivity charge pump for reception Plastic 20-pin dual in line package (Suffix: -P) Plastic 20-pin flat package (Suffix: -PF)
PLASTIC PACKAGE FPT-20P-M01
PIN ASSIGNMENT
GND 1 2 3 4 5 6 7 8 9 10 TOP VIEW 20 19 18 17 16 15 14 13 12 11 Data Data LE fin2 VCC2 fp LD2 VP2 DO2 BS2
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating Symbol VCC Power Supply Voltage VP Output Voltage Output Current Storage Temperature NOTE: VOUT IOUT TSTG VCC to 10.0 -0.5 to VCC +0.5 10 -55 to +125 V mA C Value -0.5 to 7.0 Unit V
OSCIN OSCOUT fin1 VCC1 fr LD1 VP1 DO1 BS1
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Copyright
(c)1994 by FUJITSU LIMIED 1
MB1519
MB1519 BLOCK DIAGRAM
7 9 10 6 15 14 12 11
8 Charge Pump Charge Pump
13
1
Phase Detector
fp monitor output selector
Phase Detector
16
TRANSMIT SECTION Binary 11-bit Programmable Counter
RECEPTION SECTION Binary 11-bit Programmable Counter
20-bit latch
Reference Counter (512, 1024)
20-bit latch
Binary 7-bit Swallow Counter
Binary 7-bit Swallow Counter
Latch Selector
23-bit shift register
CNT
Crystal Oscillator 5 Prescaler Prescaler Schmitt Circuit Schmitt Circuit Schmitt Circuit
4
2
3
17
18
19
20
2
MB1519
BLOCK DESCRIPTIONS
TRANSMIT/RECEPTION BLOCK
* 20-bit latch * Programmable divider consisting of: Binary 7-bit swallow counter (Divide ratio: 0 to 127) Binary 11-bit programmable counter (Divide ratio: 16 to 2047) * Phase detector with phase polarity change function * 600MHz dual modulus prescaler (Divide ratio: 64/65) * Charge pump
COMMON BLOCK
* 23-bit shift register * Programmable divider consisting of: Reference counter (Divide ratio: 512, 1024) (Divide frequency = 25kHz, 12.5kHz (Crystal oscillator frequency = 12.8MHz) * Crystal oscillator * fp monitor output selector * Latch selector * Schmitt circuits * Analog switches
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MB1519
PIN DESCRIPTIONS
Pin No. Pin Name 1 2 3 GND OSCIN OSCOUT
I/O - I O Ground.
Descriptions
Oscillator input pin. Oscillator output pin. A crystal is connected between OSCIN pin and OSCOUT pin. Prescaler input pin of transmit section. The connection with VCO should be AC connection. Power supply voltage input pin of transmit section. When power is OFF, latched data of transmit section is cancelled. Monitor pin for programmable reference divider output. Lock detect signal output pin of transmit section. Condition Lock Unlock LD pin output level H L
4
fin1
I
5
VCC1
-
6 7
fr LD1
O O
8 9
VP1 DO1
- O
Power supply voltage input for charge pump and analog switch of transmit section. Charge pump output pin of transmit section. Phase characteristics of the phase detector can be reversed depending upon FC-bit setting. Analog switch output pin of transmit section. Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is connected to this pin. Analog switch output pin of reception section. Usually this pin is high-impedance state. During SW is ON (LE = high), charge pump output is connected to this pin. Charge pump output pin of reception section. Phase characteristics of the phase detector can be reversed depending upon FC-bit setting. Power supply voltage input for charge pump and analog switch of reception section. Lock detect signal output pin of reception section. Condition Lock Unlock LD pin output level H L
10
BS1
O
11
BS2
O
12
DO2
O
13 14
VP2 LD2
- O
15
fp
O
Monitor pin for programmable divider output. This pin outputs divided frequency of transmit section or reception section depending upon FP bit setting. FP bit H L Output Transmit section (fp1) Reception section (fp2)
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MB1519
PIN DESCRIPTIONS (Continued)
Pin No. Pin Name 16 VCC2 I/O - Descriptions Power supply voltage input pin for reception section, programmable reference divider, shift register, and crystal oscillator. When power is OFF, latched data of reception section and reference counter is cancelled. Prescaler input pin of reception section. The connection with VCO should be AC conneciton. Load enable input pin. This pin involves a schmitt trigger circuit. When this pin is high, the data stored in the shift register is transferred into the latch depending on a control data. At this moment, charge pump output signal is output from BS pin since internal analog swith becomes ON. Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit. The stored data in the shift register is transferred to either transmit section or reception section depending upon a control data. Control bit data H L The destination of data Latch of transmit section Latch of reception section
17
fin2
I
18
LE
I
19
Data
I
20
Clock
I
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit. On rising edge of the clock shifts one bit of data into the shift register.
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC / R (A < N)
fVCO: Output frequency of external voltage controlled ocillator (VCO) M: N: A: Preset divide ratio of dual modulus prescaler (64) Preset divide ratio of binary 11-bit programmable counter (16 to 2047) Preset divide ratio of binary 7-bit swallow counter (0 A 127)
fOSC: Reference oscillator frequency R: Preset divide ratio of reference counter (512 or 1024)
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MB1519
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of transmit section and programmable divider of reception section are controlled individually. Serial data of binary data is input into Data pin. On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high, the data stored in the shift register is transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting. Control data H L Destination of serial data Latch of transmit section Latch of reception section
SHIFT REGISTER CONFIGURATION
Control bit LSB Data Flow MSB
1 C N T
2 R E F
3 F P
4 D M Y
5 F C
6 A 1
7 A 2
8 A 3
9 A 4
10 A 5
11 A 6
12 A 7
13 N 1
14 N 2
15 N 3
16 N 4
17 N 5
18 N 6
19 N 7
20 N 8
21 N 9
22 N 10
23 N 11
N1 to N11 A1 to A7 FC DMY FP REF CNT
: Divide ratio of the programmable counter setting bit (16 to 2047) : Divide ratio of the swallow counter setting bit (0 to 127) : Phase control bit of the phase detector : Dummy bit (sets to low) : Output of the programmable divider control bit (fp1 or fp2) : Divide ratio of the reference counter setting bit (512 to 1024) : Control bit
SERIAL DATA INPUT TIMING
* t1 , t2, t3, t4, t5 1s
Data
N11 = MSB
N10
N1
A7
REF = LSB
C: Control bit
Clock
LE t2 t1 t5 t3 t4
On rising edge of the clock shifts one bit of the data into the shift register.
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MB1519
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide Ratio (N) 16 17 N 11 0 0 N 10 0 0 N 9 0 0 N 8 0 0 N 7 0 0 N 6 0 0 N 5 1 1 N 4 0 0 N 3 0 0 N 2 0 0 N 1 0 1
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 16 is prohibited. Divide ratio (N) range = 16 to 2047
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide Ratio (A) 0 1 A 7 0 0 A 6 0 0 A 5 0 0 A 4 0 0 A 3 0 0 A 2 0 0 A 1 0 1
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127 DMY : DUMMY BIT INPUT This bit is set to low in operation. REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT H = 512 (fr = 25.0 kHz) L = 1024 (fr = 12.5 kHz) FP : OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT H = fp pin (15 pin) outputs programmable divider output frequency (fp1) of transmit section. L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of reception section. : PHASE CONTROL BIT OF THE PHASE DETECTOR Output of charge pump is selected by FC pin.
FC
FC = H fr > fp fr = fp fr < fp VCO Polarity H Z L (1)
FC = L L Z H (2) VCO Output Frequency
(1)
Note: Z = High-impedance Depending upon the VCO poratity, FC bit should be set.
(2)
VCO Input Voltage
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MB1519
PHASE DETECTOR OUTPUT WAVEFORM
fr
fp
tW
tW
LD
(FC bit = High) H DO Z L
(FC bit = Low) DO Z
Note:
* Phase difference detection range = -2 to +2 * LD output becomes low when phase difference is tW or more. LD output becomes high when phase difference less than tW is reperated 3 times or more. (e. g. tW = 625 to 1250 ns, foscin = 12.8 MHz) * Spike apperance depends on the charge pump characteristics. The spike is output to diminish the dead band. * When fr > fp or fr < fp, spike might not generate depending up the VCO characteristics.
8
MB1519 ANALOG SWITCH
ON/OFF of the analog switch is controlled by the combination of the control data and LE signal. When the analog switch is ON, BS1, BS2 pin output the charge pump output (D01, D02). When analog switch is OFF, BS pin is set to high impedance. Control data = H Divide ratio of transmit section is set LE = H Analog switch of transmit section Analog switch of reception section ON OFF LE = L OFF OFF Control data = L Divide ratio of reception section is set LE = H OFF ON LE = L OFF OFF
When a analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL channel switching.
DO CHARGE PUMP LPF-1 LPF-2 VCO
BISW ANALOG SW
(CONTROL SIGNALE)
RECOMMENDED OPERATING CONDITIONS
Value Parameter Symbol Min VCC Power Supply Voltage VP Input Voltage Operating Temperature VIN TA VCC GND -40 - - - 8.0 VCC +85 V V C 2.7 Typ 3.0 Max 5.5 V VCC1 = VCC2 Unit Note
HANDLING PRECAUTIONS
* This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
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MB1519
ELECTRICAL CHARACTERISTICS
Value Parameter Symbol Condition Min ICC1 Power Supply Current ICC2 fin Operating Frequency OSCIN fOSC VCC = 2.7 to 4.0V, 50 fin Input Sensitivity OSCIN High-level Input Voltage Low-level Input Voltage High-level Input Current Low-level Input Current Input Current High-level Output Voltage Low-level Output Voltage High-impedance Cutoff Current Except fin and OSCIN VOSC VIH VIL IIH IIL IOSC VOH VOL IOFF IOH IOL IOH Output Current DO1 IOL IOH DO2 IOL Analog Switch ON Resistance Notes: RON VCC = 3V - - 6 25 - - VCC = 3V VP = 6V - - 12 -3 - - VP = 6V VP = VCC to 8.0V VOOP = GND to 8.0V VCC = 3.0V Vfin VCC = 4.0 to 5.5V, 50 -4 0.5 VCCx0.7+0.4 - - - - 2.2 - - - - - 1.0 -1.0 50 - - 4 - - V VCCx0.3-0.4 - - - - V 0.4 A A VPP - -8 12.8 - 20 0 dBm fin Reception section is active. Transmit/reception section are active. - - Typ 5.5 11.0 Max 8.0 mA 16.0 Unit
10
-
600 MHz
Data, Clock LE OSCIN Except DO and OSCOUT
DO
-
-
1.1
Except DO and OSCOUT
-1.0 1.0 -
- - -1
- - - mA
: fin = 600MHz, OSCIN = 12.8MHz, VCC1 = VCC2 = 3.0V. The remaining input pins are grounded and output pins are open. : AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
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MB1519
TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)
VP1
VCC1
X'tal
0.1F 1000pF P.G 8 50
0.1F GND 5 4 3 2 1
MB1519
13 P.G 1000pF 50 VP2
15
16
17
18
19
20
fp Oscilloscope VCC2 0.1F 0.1F
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MB1519
APPLICATION EXAMPLE
Output VCO LPF Lock Detector 3V 6V
From Controller
1000pF
0.1F
0.1F
20 Clock
19 Data
18 LE
17 fin2
16 VCC2
15 fp
14 LD2
13 VP2
12 D02
11 BS2
MB1519
GND 1
OSCIN 2
OSCOUT 3
fin1 4
VCC1 5 3V
fr 6
LD1 7
VP1 8 6V
D01 9
BS1 10
X'tal C1 C2 0.1F 0.1F Lock Detector 1000pF
Output VCO LPF
Note:
VP1, VP2 C1, C2 Clock, Data, LE X'tal
: 8 V max. : depends on the crystal oscillator. : involve the schmitt circuit. When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation. : 12.8MHz
12
MB1519
PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M02)
.970 +.008 (24.64 +0.20 ) -0.30 -.012
15MAX
INDEX-1 .244.010 (6.200.25) .300(7.62) TYP
INDEX-2 .034 +.012 -0 (0.86+0.30 ) -0 .050 +.012 -0 (1.27 +0.30 ) -0 .010.002 (0.250.05)
.172(4.36)MAX
.118(3.00)MIN .100(2.54) TYP .018.003 (0.460.08)
.020(0.51)MIN
.050(1.27) MAX
(c)1991 FUJITSU LIMITED D20003S-3C
Dimensions in inches (millimeters)
13
MB1519
PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01)
+.010 +0.25 .500 (12.70 ) -.008 -0.20
.089(2.25) MAX (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT)
.307.016 (7.800.40) INDEX .209.012 (5.300.30) +.016 +0.40 .268 (6.80 ) -.008 -0.20
.020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) O.005(0.13) M +.002 +0.05 .006 (0.15 ) -.001 -0.02
Details of "A" part "A" .008(0.20)
.004(0.10) .450(11.43) REF
.020(0.50) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters)
(c)1991 FUJITSU LIMITED F20003S-5C
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MB1519
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The Information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.
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MB1519
For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT, 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211, Japan Tel: (044) 754-3753 FAX: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 FAX: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10, 63303 Dreieich-Buchschlag, Germany Tel: (06103) 690-0 FAX: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No.51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 FAX: 336-1609
(c) FUJITSU LIMITED 1994
Printed in Japan DS04-21314-1E
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